The present invention relates to a semiconductor circuit technology and, more particularly, to an exponential function generator and a variable gain amplifier (VGA) employing the same.
In a wireless communication system, a receiver may receive a signal that experiences wide variations in signal power. In receivers such as are used in a wideband digital code division multiple access (CDMA) mobile station, it is necessary to control the power of the demodulated signal for proper signal processing. Moreover, in transmitters such as are used in a CDMA mobile station, it is indispensable to control the transmit power in order to avoid excessive interference to other mobile stations. These same power control considerations apply to narrowband analog frequency modulation (FM) wireless communication system transmitters and receivers.
Dual-mode CDMA/FM wireless communications systems should provide power control of transmitted and received signals of both digital CDMA and analog FM modulation. In these dual-mode mobile stations, the control process is complicated by the differing dynamic ranges and industry regulation standards associated with the CDMA and FM signals. Therefore, the provision of separate automatic gain control (AGC) circuitry for both the CDMA and the FM signals increases the complexity and expense of such dual-mode mobile stations. Accordingly, it is desired to provide AGC circuitry capable of operating upon both the CDMA and FM signals.
A variable gain amplifier (VGA), which is one of the AGC circuits, provides a gain in proportion to a control voltage. The VGA provides an exponential voltage gain as a function of linear increases in the applied control voltage thereby providing an approximately linear power gain in decibels (dB) in direct proportion to linear increases in the applied control voltage. The VGA can be used in many applications including receivers and transmitters.
Referring to FIG. 1, there is shown a block diagram of a conventional variable gain amplifier (VGA) 100 included in a receiver of a dual-mode CDMA/FM mobile station, which is found in U.S. Pat. No. 5,880,631, entitled xe2x80x9cHIGH DYNAMIC RANGE VARIABLE GAIN AMPLIFIERxe2x80x9d issued Mar. 9, 1999, and briefly summarized herein as representative of the prior art.
As shown in FIG. 1, the VGA 100 comprises an input stage 120 and two cascaded current amplifiers 160A and 160B. The current amplifiers 160A and 160B are successively cascaded to increase the dynamic range of the VGA 100 and the number of current amplifiers can be adjusted, as necessity requires.
The input stage 120 includes a separate FM input stage 121 and CDMA input stage 122 with respective input ports 171 and 170. The FM input stage 121 and the CDMA input stage 122 are alternately connected to the current amplifier 160A through switches 123, which are controlled by a CDMA/FM mode select signal.
The VGA 100 also employs bias ports 110, 130, 150A and 150B for control voltages to be applied to the VGA 100. The gain of each stage is controlled by control voltages, which, for example, may be generated by receiver detection circuitry that determines the signal strength. Each stage is comprised of a variety of components, including an active device such as a transistor.
Since it operates with a low supply voltage, about 3.6 V, the input stage 120 converts an input voltage signal to a current signal to prevent the VGA active devices from operating in their non-linear region, and distorting the input signal.
Meanwhile, FIG. 1 provides the bias port 130 coupled to a transconductance bias control circuit 140, which will be described later.
Referring to FIG. 2, there is shown a diagram of the CDMA input stage 122 of FIG. 1, which includes a Gilbert cell attenuator 226 and a variable transconductance amplifier 227 and serves four functions.
First, the variable transconductance amplifier 227 converts the input voltage signal to a current signal. Second, the combination of the variable transconductance amplifier 227 and the Gilbert cell attenuator 226 permits variable amplification of the signal, which may be varied exponentially by linearly adjusting control voltages at the bias port 110. Third, increased emitter degeneration in the variable transconductance amplifier 227 reduces the intermodulation distortion (IMD) of the VGA 100 when the input voltage signal is large and the IMD would be most prominent. That is, as the emitter degeneration in the variable transconductance amplifier 227 is increased, the transconductance, and thus the IMD, of the CDMA input stage 122 is decreased. Fourth, decreased emitter degeneration in the variable transconductance amplifier 227 improves the noise feature of the VGA 100 when the input voltage signal is small and noise performance is the most critical. Namely, as the emitter degeneration in the variable transconductance amplifier 227 is decreased, the transconductance of the CDMA input stage 122 is increased, improving the noise feature of the receiver.
The variable transconductance amplifier 227 is comprised of two bipolar junction transistors (BJTs) 235 and 236, two current sources 238 and 239, and a field effect transistor (FET) 237. The current sources 238 and 239 are serially connected to the emitters of the BJTs 235 and 236, respectively. The source connection 228 and drain connection 229 of the FET 237 are respectively connected to the emitters of the BJTs 235 and 236. The balanced signal at the VGA input port 170 is applied to the bases of the BJTs 235 and 236. The balanced current output of the variable transconductance amplifier 227 flows from the collectors of the BJTs 235 and 236.
The transconductance of the variable transconductance amplifier 227 may be adjusted by varying the emitter degeneration of the BJTs 235 and 236. As a result, the gain of the VGA 100 may be varied. The emitter degeneration of the BJTs 235 and 236 is created by varying the channel resistance of the FET 237. The FET 237 is operated like a variable resistor in its ohmic region and provides variable emitter degeneration for both of the BJTs 235 and 236. The drain-source bias voltage of the FET 237 must therefore be less than the knee voltage of the FET 237. The channel resistance may be varied by adjusting the bias across the gate-source junction of the FET 237 by varying the voltage applied at a bias port 124. The transconductance of the variable transconductance amplifier 227 can be increased by decreasing the channel resistance of the FET 237.
The differential output currents of the variable transconductance amplifier 227 are coupled to the Gilbert cell attenuator 226. The Gilbert cell attenuator 226 varies the current amplitude of a signal applied to its inputs. The Gilbert cell attenuator 226 contains a first pair of BJTs 231 and 234, and a second pair of BJTs 232 and 233. The attenuation level of the Gilbert cell attenuator 226 is established by a control voltage applied at the bias port 110.
The Gilbert cell attenuator 226 attenuates the output current of the variable transconductance amplifier 227 when the first pair of BJTs 231 and 234 are biased by the control voltage applied to the bias port 110 so that a component of the variable transconductance amplifier""s output current flows through the first pair of BJTs 231 and 234 rather than through the second pair of BJTs 232 and 233. Hence the balanced currents at an output port 190 of the Gilbert cell attenuator 226 are diminished.
The configuration of the FM input stage 121 is similar to that of the CDMA input stage 122 described in FIG. 2 except that the FET 237 is replaced by a fixed resistance. As previously mentioned, the fixed resistance of the FM input stage 121 provides a fixed transconductance because industry standards, such as IS-95, allow compression of the input signal at a much lower input level than that of the CDMA input signal.
Referring to FIG. 3, there is provided a diagram of the transconductance bias control circuit 140 of FIG. 1.
As shown in FIG. 3, the transconductance bias control circuit 140 includes an exponential function generator 360, a first and a second operational amplifier circuit 353 and 354, a low pass filter 352 and a current source 341.
The exponential function generator 360 converts the control voltage applied at the bias port 130 to two output currents flowing from an output node 358 of the exponential function generator 360 to the first operational amplifier circuit 353. The ratio of the amplitudes of these currents is exponentially proportional to the control voltage.
Referring to FIG. 4, there is illustrated a diagram of the exponential function generator 360, which comprises a differential amplifier 465 provided with the control voltage at the bias port 130 and a pair of FET current mirrors 474 driven by outputs of the differential amplifier 465. The differential amplifier 465 includes a parallel pair of BJTs 461 and 462 whose bases are connected to the bias port 130 and a current source 472 connected to the pair of BJTs 461 and 462. The pair of FET current mirrors 474 includes four FETs 464, 466, 468 and 470. Due to an exponential input voltage-output current relationship of the BJTs 461 and 462, the ratio of their collector currents is proportional to the differential base voltage between the BJTs 461 and 462, which is determined by the control voltage signal. Thus, the linear differential voltage change across the bias port 130 is translated to an exponentially related current at the output node 358. The current mirrors 474 simply take the exponentially related current generated by the pair of BJTs 461 and 462 and provide it for use throughout the differential amplifier 465.
Referring back to FIG. 3, the first and the second operational amplifier circuits 353 and 354 act in cooperation with the exponential function generator 360 to control the channel resistance of the FET 237 of FIG. 2. The first operational amplifier circuit 353 employs a master FET 344, which is preferably identical to the FET 237, a reference resistor 346 and a differential operational amplifier 348. The output currents from the exponential function generator 360 are coupled to the master FET 344 and the reference resistor 346. The differential operational amplifier 348 forces the voltage across the drain and source terminals of the master FET 344 and the terminals of the reference resistor 346 to be equal by varying the bias voltage applied to the gate of the master FET 344. The bias voltages applied to the gates of the FET 237 and the master FET 344 are generally equal. However, the gate bias voltage applied to the FET 237 through the bias port 124 is low pass filtered to prevent thermal noise from the transconductance bias control circuit 140 from being injected onto the FET 237. The low pass filtering is accomplished by a low pass filter 352 formed by series resistor 350 and shunt capacitor 351.
The second operational amplifier 354 includes a non-inverting, unity gain operational amplifier 349 and resistors 345 and 347, that sense the drain-source voltage across the FET 237 via the source connection 228 and the drain connection 229. The second operational amplifier circuit 354 forces the master FET 344 and the FET 237 to have the same source voltage.
The exponential function generator 360 and the current source 341 connected around the master FET 344 and the reference resistor 346 are designed so that the voltage drop across the reference resistor 346, and hence across the drain-source of the master FET 344, is less than the FET""s knee voltage. As a result, the operation of the first and the second operational amplifier circuits 353 and 354 force the FET 237 and the master FET 344 to operate at similar quiescent points in their ohmic regions. Therefore, the channel resistances of both of the FET 237 and the master FET 344 are generally identical and vary exponentially with a linearly adjusted control voltage applied to the bias port 130.
Referring to FIG. 5, there is illustrated a diagram of the current amplifiers 160A and 160B of FIG. 1. The input of the current amplifier 160 as shown in FIG. 5 may be coupled to the output of the input stage 120 or the output of another current amplifier. The current amplifier 160 comprises a Darlington differential amplifier 510, a cascode differential amplifier 520 and a tail current generator 570. The current amplifier 160 is biased by power supplies and current sources 596 and 598.
The Darlington differential amplifier 510 includes BJTs 580, 586, 588 and 594 and resistors 582, 584, 590 and 592 in the topology shown in FIG. 5 such that the Darlington differential amplifier 510 has a resistive shunt-series feedback to provide an enhanced current gain and process variation insensitivity.
The cascode differential amplifier 520 includes BJTs 500, 502, 504 and 506 in the topology of a differential current mirror, which allows the gain of the current amplifier 160 to be varied by varying tail currents. The cascode differential amplifier 520 provides a translinear loop, which provides variable current amplification according to the ratio of the tail currents generated by the tail current generator 570.
The gain of the current amplifier 160 is controlled by the tail current generator 570. The tail current generator 570, through a differential port, is connected to both of the Darlington differential amplifier 510 and the cascode differential amplifier 520. The current amplification of the current amplifier 160 may be varied exponentially by using the control current generated by the exponential function generator 360 of FIG. 4 and applied to the control ports 150. For reference, the tail current generator 570 includes an exponential function generator and a pair of bipolar current mirrors. Each of the bipolar current mirrors includes a plurality of resistors and a multiplicity of BJTs.
As described above, since the conventional VGA includes BJTs in each component thereof, it is formed by a BiCMOS manufacturing process. In particular, the exponential function generator having exponentially varying gain can readily convert the control voltage to an exponential current by using features of the BJT device itself. Therefore, the reason why the BiCMOS manufacturing process is used instead of a CMOS manufacturing process, even though the CMOS process can achieve low cost of production and high integration, is that it is difficult to implement an appropriate exponential function although a device of a large size is used since the transconductance of a CMOS device is very small and, thus, BJT""s are inevitably used. Further, it is difficult to attain BJT features of acting amplification through the use of the CMOS manufacturing process.
Meanwhile, the exponential function generator is widely applied to other analog systems in addition to the before-mentioned VGA and, therefore, it is required to form the exponential function generator by using the CMOS manufacturing process.
It is, therefore, a primary object of the present invention to provide an exponential function generator capable of attaining an appropriate exponential function through the use of a CMOS manufacturing process.
Another object of the present invention is to provide a variable gain amplifier employing the exponential function generator, which can be implemented by a CMOS manufacturing process.
In accordance with one aspect of the present invention, there is provided an exponential function generator comprising a first and a second curve generator for producing signals varying with different slopes by sampling an inputted control voltage; and an adder for summing up the signals outputted from the first and the second curve generators to thereby output a voltage signal having an approximated exponential function value.
In accordance with another aspect of the present invention, there is provided a variable gain amplifier embodied by a CMOS process, comprising an input stage for amplifying differential input signals to thereby output voltage signals having a limited fixed gain value; an exponential function generator including a first and a second curve generator which produce signals varying with different slopes by sampling an inputted control voltage, and summing up the signals outputted from the first and the second curve generators to thereby output a signal having an approximated exponential function value; a control current generator for producing an exponential control current in response to the output signal of the exponential function generator; and a variable voltage amplifier for performing variable gain amplification of the voltage signal outputted from the input stage in response to the exponential control current.
In accordance with the present invention, the exponential function generator is implemented by using a CMOS manufacturing process. Since it is difficult for CMOS devices to attain an exponential function by themselves, the present invention employs a scheme of generating two voltage signals varying with different slopes for a control voltage and summing up the two voltage signals so as to obtain an approximated exponential function. Meanwhile, in accordance with the present invention, the VGA including the inventive exponential function generator is designed capable of being implemented by employing the CMOS manufacturing process. That is, the present invention performs only fixed gain amplification at an input stage by considering the deterioration of features of CMOS devices, linearly changes the gain by providing an exponential control current to a variable gain cell, e.g., a differential voltage amplifier, performing the practical gain variation for the bias control of the variable gain cell, and constructs a load by using FETs operating in an ohmic region to perform a stabilized operation regardless of variations in external factors such as temperature, manufacturing processes and so on.